On account of the physical conditions when fabricating integrated semiconductor chips at the wafer level and during the further fabrication steps until the semiconductor memory components are in the package, it is virtually impossible to avoid some of the multiplicity of memory cells in the integrated semiconductor memory components already being defective during or after fabrication. In order to enable correct and reliable operation of these semiconductor memory components in the application system environment in which they are used, for example in mobile telephones, notebooks, PCs etc., the defective memory cells are often replaced with redundant memory cells which are likewise present in the integrated semiconductor memory component.
In this case, DE 10 2004 039 831 adopts the approach of arranging redundant memory cells for the integrated semiconductor memory component affected, which has a volatile memory such as a dynamic RAM (DRAM) memory, in the logic chip of a multichip module, said logic chip being in the form of a digital signal processor or a processor/CPU, in particular, rather than in the volatile memory itself. The nonvolatile memory area used may also be, in particular, in the form of an electrically programmable connection for permanently storing a data item, which is also referred to as an E-fuse. In this case, a diversion is effected in such a manner that, when the defective memory cells are accessed, a diversion to these E-fuses is effected. In this case, it is disadvantageous that such E-fuses are often not available in the multichip module used or would have to be additionally provided, which is often not possible.
DD 239 061 exhibits a multichip hybrid memory containing two memory chips and two programmable logic blocks. The latter identify defective columns and rows and switch back and forth between a basic memory and a redundancy chip.
US 2004/0006404 exhibits “ID” memories which store information relating to the production, testing and performance of a chip. In U.S. Pat. No. 4,473,895, main memory cells and redundancy memory cells are activated at the same time.